In overlay critical lithography steps, non-linear wafer deformation is one possible source of non-uniformity. As the overlay budgets shrink with shrinking ground rules, and the processes get more aggressive, e.g., high aspect ratio etching or deposition of exotic materials, across wafer non-uniformity of several process steps result in non-uniform stress being applied to the wafer. This results in non-linear wafer deformation.
This can be partly corrected by non-linear alignment models, but this is often found insufficient mainly at the wafer edge. In addition, full wafer overlay measurements can be done to establish an overlay grid map that can be sent to the exposure tool in a feed-back loop.
With the ever increasing need for smaller and denser structures on a semiconductor wafer, the allowable positioning difference between, e.g., an actual processed resist film and a previously formed layer decreases as well. The tolerable overlay budget can influence the throughput through a fabrication unit, as semiconductor wafers which are outside the specification of the tolerable mismatch have to be reworked or otherwise sorted out.
Overlay accuracy depends, among other factors, upon the alignment of the semiconductor wafer with an exposure tool. Usually a mask projection step in an exposure tool is performed in different exposure fields which are arranged next to each other on the semiconductor wafer. Prior to exposure, the wafer is aligned to the projection mask of the exposure tool by use of an alignment system in the exposure tool.
In order to judge overlay stability, several semiconductor wafers are measured by an overlay metrology tool. The result is used for determining the actual overlay accuracy with respect to the processed wafer.
For these and other reasons, there is a need in the art to improve on alignment calculation.